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Investigating the use of approximate circuits in reducing the power consumption of chips
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Abstract: (145 Views) |
| With the advent of technology, the design of integrated circuits with high density and reduced transistor sizes has posed significant challenges. One of the most complex issues is improving efficiency and optimizing power consumption of these circuits. It is predicted that by 2025, more than 50 billion devices will be connected to the internet. The need for devices with optimized power consumption (i.e., long battery life) has slowed down the growth and development of the Internet of Things. Therefore, there is a growing trend towards the use of System on Chips (SoC) which have suitable reusability capabilities. In all applications, precise results are not necessary, and having acceptable results is sufficient. Approximate computations are an efficient approach to design fault-tolerant applications by balancing accuracy, area, delay, and power consumption based on computational requirements. By sacrificing accuracy, approximate computations can achieve significant improvements in speed, power consumption, and area. This technique can be applied at various design levels, including software, architecture, processor, memory, and circuit. In this article, we provide a review of the methods for reducing power in approximate circuit designs. |
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| Keywords: Approximate computations, Approximate Computing Circuits, Internet of Things (IoT), System on Chips (SoC), Power Consumption |
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Full-Text [PDF 854 kb]
(71 Downloads)
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Type of Study: Scientific-extension |
Subject:
Special
Received: 2025/06/1 | Accepted: 2025/03/5 | Published: 2025/03/5
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