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سلول حافظه ۱۲ ترانزیستوری SRAM جدید با سرعت بالا و توان مصرفی کم
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Abstract: (1481 Views) |
| Power and speed are two parameters which have attracted the designer’s trends in the integrated circuit designs. The memory blocks and specially the SRAM cells consume high chips area and consequently these cells optimization can increase the whole system performance. In this paper, a new twelve transistors (12T) SRAM cell is proposed that improves read and write speed and stability, along with lower power consumption speeds so that overall static reading margin is up to 19% better than 12 transistor memory cells. And it has a 43% improvement over a conventional six-transistor SRAM cell, and also an average reading and writing speed of about 30% compared to a 12-transistor cell, as the number of transistors increased compared to the six-transistor cell, the power consumption decreased by about 40% and compared to the 12-cell transistor cell, the power consumption decreased dramatically by 80% for best efficiency. The simulation results show progress in improving energy loss and reducing the reading and writing noise margins compared to the previous design. |
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| Keywords: memory cell, static memory, noise margin, memory stability |
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Full-Text [PDF 10372 kb]
(1139 Downloads)
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Type of Study: Scientific-extension |
Subject:
Special
Received: 2020/11/14 | Accepted: 2020/09/20 | Published: 2020/09/20
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